ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH
WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH
WILL BE UNINTERRUPTED OR ERROR-FREE.

//****************************************************************
quartusii-12.1-0.dp1-readme.txt
Readme file for Quartus II 12.1 Patch 0.dp1
Copyright (C) Altera Corporation 2012 All right reserved.
Patch created on November 30 2012
Patch Case#: 87250
//****************************************************************

This patch addresses known software issues for Stratix V, Arria V and
Cyclone V devices in the Quartus II software version 12.1.

The device patches are cumulative.

=============================================
The following issues are addressed in 0.dp1:
=============================================

--------------------
Issue 1 (case 86040)
--------------------
TCO reported for wide data widths in M20K blocks with registered
outputs in Stratix V devices is incorrect

TCO values reported by the TimeQuest Timing Analyzer for Stratix V
M20K blocks that use more than 16 bits and that have registered
outputs may be pessimistic. TCO values of output register bits 16 to
39 reported by TimeQuest can be pessimistic by as much as 500 ps. TCO
values for bits 0 to 15 are reported correctly.

For up-to-date information about Stratix V timing model issues found
in the Quartus II software version 12.1, refer to solution number
rd11162012_922 in the Altera Knowledge Base.

--------------------
Issue 2 (case 86202)
--------------------
Timing paths from Stratix V DSP input ports are not analyzed in some
circumstances.

In designs that target Stratix V devices, if DSP outputs are
registered, but the RESULT ports are disconnected, which is common
among filters, then any paths from the DSP input port to the DSP
output register are not analyzed for timing.

For up-to-date information about Stratix V timing model issues found
in the Quartus II software version 12.1, refer to solution number
rd11162012_922 in the Altera Knowledge Base.

--------------------
Issue 3 (case 86732)
--------------------
Timing delays reported from QCLK to SCLK for QCLKs 73 to 91 in Stratix V
devices are incorrect

For designs that target Stratix V devices, the timing delay from
Regional Clocks (QCLKs) to Spine Clocks (SCLKs) on the right center
and left center of the device (QCLKs 73 to 91) is incorrectly reported
as zero. The actual delay for speed grade 3 devices at 85°C is
approximately 1 ns.

For up-to-date information about Stratix V timing model issues found
in the Quartus II software version 12.1, refer to solution number
rd11162012_922 in the Altera Knowledge Base.

--------------------
Issue 4 (case 86556)
--------------------
Quartus II might trigger the following internal error for Cyclone V E50
designs with HMC instantiated:

Internal Error: Sub-system: ASM, 
File: /quartus/comp/asm/asm_dev_cyclone5.cpp, Line: 1238
ASM_MODEL::s_atom_asm_index != -1

--------------------
Issue 5 (case 59936)
--------------------
This patch enables unbonded CMU for Arria V C3 device F896 package
under INI control. Please contact your Altera FAE/AE if you need
this support.

--------------------
Issue 6 (case 83655)
--------------------
Any Stratix V EMIF interface based on an F9 die that uses pins in
banks 8E or 7E will not function correctly in hardware.
 
Root Cause: Levelling Delay Chain to IO bank connections were swapped
for banks 8E and 7E in the software model.

--------------------
Issue 7 (case 83710)
--------------------
Arria V RX Equalizer Setting mapping in Quartus II software is
incorrect.

--------------------
Issue 8 (case 84782)
--------------------
Can't select /64 refclk frequency for 10312.5Mbps in Stratix V Low
Latency PHY IP from Mega Wizard.

--------------------
Issue 9 (case 84923)
--------------------
PLL code might cause errors in post-fit flow for parameters nreset,
fractional_carryout, and m_cnt_prst. This patch prevents those errors
and recognizes the valid parameter values.

--------------------
Issue 10 (case 85969)
--------------------
Quartus II software might trigger the following internal error in
fitter stage for Partial Reconfiguration revisions:

Internal Error: Sub-system: FITCC,
File: /quartus/fitter/fitcc/fitcc_pr_bits_utility.cpp, Line: 895
pr_region == parent_region_id || parent_region_id == MSF_STATIC_REGION_ID

The problem might occur for PR designs that use both reconfigurable, and
non-reconfigurable LogicLock regions. The error is caused by a false
positive in a post-routing verification step. This patch fixes the
faulty logic in the verification step.

--------------------
Issue 11 (case 81664)
--------------------
Internal Error: Sub-system: ASMDB, 
File: /quartus/db/asmdb/asmdb_param.cpp, Line: 522
iter != m_enum_map->end()

--------------------
Issue 12 (case 86164)
--------------------
This patch supports junction temperature QSF settings for Cyclone V
devices.

--------------------
Issue 13 (case 86260)
--------------------
Unexpected signal behavior on the pins within 8A and 8B IOBANK of
Arria V F780 package due to one of the VREF pads not being configured
correctly.

--------------------
Issue 14 (case 86274)
--------------------
This patch provides the following support:
1. Exposes a user-requested ZQ calibration port on UniPHY, similar to
   user refresh.  The port is activated by setting
   alt_mem_if_pingpong_ctl=on, which increases the max pending
   read/write commands that can be handled by the controller (for
   efficiency reasons).

2. Exposes a set of ports for the refresh controller component.  These
   ports consist of the tbp_empty, cmd_gen_busy, and
   sideband_in_refresh signals.  These signals are connected to the
   refresh controller by the customer when INI
   alt_mem_if_enable_refctrl=on is set.

--------------------
Issue 15 (case 86377)
--------------------
This patch adds support for Arria V 5AGXFB3H4F35C4ES under
dev_password control.  Please contact your Altera FAE/AE if you need
this device support.

--------------------
Issue 16 (case 86494)
--------------------
Quartus II software requires a developer license when
RBCGEN_ERROR_TO_CRITICAL_WARNING INI is used.

--------------------
Issue 17 (case 86375)
--------------------
Analog reconfig IP: Preemphasis - pre-tap and 2nd post-tap mappings are
not correct in Quartus II version 12.1.

--------------------
Issue 18 (case 86651)
--------------------
Any Arria V part based on C3 die that uses the right side Levelling
Delay Chains will not function as expected.

Root Cause: Connections from DLL to the Levelling Delay Chains on the
right side were using the wrong DLL output ports.

--------------------
Issue 19 (case 83680)
--------------------
Internal Error: Sub-system: ASMDB, 
File: /quartus/db/asmdb/asmdb_offset_cache.cpp, Line: 860
Illegal setting

--------------------
Issue 20 (case 84482)
--------------------
This patch enhances the UniPHY calibration algorithm for all V-series
families. The enhancement adds an extra read calibration after write
calibration, which provides better centering of the read strobe/clock
within the read data window. This enhancement improves robustness at
the highest supported frequencies such as 933MHz DDR3 on Stratix V C2
devices and 800MHz DDR3 on Stratix V 800MHz C3 devices.


Caution - This patch is not a complete version of the Quartus II
          software.  You must have previously installed the Quartus II
          12.1 before installing this patch.