ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH
WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH
WILL BE UNINTERRUPTED OR ERROR-FREE.
//****************************************************************
quartusii-12.1-0.dp5-readme.txt
Readme file for Quartus II 12.1 Patch 0.dp5
Copyright (C) Altera Corporation 2012 All right reserved.
Patch created on January 4, 2013
Patch Case#: 87250
//****************************************************************
This patch addresses known software issues for Stratix V, Arria V and
Cyclone V devices in the Quartus II software version 12.1.
The device patches are cumulative.
=============================================
The following issues are addressed in 0.dp1:
=============================================
--------------------
Issue 1 (case 86040)
--------------------
TCO reported for wide data widths in M20K blocks with registered
outputs in Stratix V devices is incorrect
TCO values reported by the TimeQuest Timing Analyzer for Stratix V
M20K blocks that use more than 16 bits and that have registered
outputs may be pessimistic. TCO values of output register bits 16 to
39 reported by TimeQuest can be pessimistic by as much as 500 ps. TCO
values for bits 0 to 15 are reported correctly.
For up-to-date information about Stratix V timing model issues found
in the Quartus II software version 12.1, refer to solution number
rd11162012_922 in the Altera Knowledge Base.
--------------------
Issue 2 (case 86202)
--------------------
Timing paths from Stratix V DSP input ports are not analyzed in some
circumstances.
In designs that target Stratix V devices, if DSP outputs are
registered, but the RESULT ports are disconnected, which is common
among filters, then any paths from the DSP input port to the DSP
output register are not analyzed for timing.
For up-to-date information about Stratix V timing model issues found
in the Quartus II software version 12.1, refer to solution number
rd11162012_922 in the Altera Knowledge Base.
--------------------
Issue 3 (case 86732)
--------------------
Timing delays reported from QCLK to SCLK for QCLKs 73 to 91 in Stratix V
devices are incorrect
For designs that target Stratix V devices, the timing delay from
Regional Clocks (QCLKs) to Spine Clocks (SCLKs) on the right center
and left center of the device (QCLKs 73 to 91) is incorrectly reported
as zero. The actual delay for speed grade 3 devices at 85°C is
approximately 1 ns.
For up-to-date information about Stratix V timing model issues found
in the Quartus II software version 12.1, refer to solution number
rd11162012_922 in the Altera Knowledge Base.
--------------------
Issue 4 (case 86556)
--------------------
Quartus II software might trigger the following internal error for
Cyclone V E50 designs with HMC instantiated:
Internal Error: Sub-system: ASM,
File: /quartus/comp/asm/asm_dev_cyclone5.cpp, Line: 1238
ASM_MODEL::s_atom_asm_index != -1
--------------------
Issue 5 (case 59936)
--------------------
This patch enables unbonded CMU for Arria V C3 device F896 package
under INI control. Please contact your Altera FAE/AE if you need
this support.
--------------------
Issue 6 (case 83655)
--------------------
External Memory Interfaces that use pins from banks 8E or 7E on the
following Stratix V devices will not function correctly in hardware.
5SEE9, 5SEEB, 5SGXEA9, 5SGXEAB, 5SGXEB9, 5SGXEBB, 5SGXMA9, 5SGXMAB,
5SGXMB9, 5SGXMBB
--------------------
Issue 7 (case 83710)
--------------------
Arria V RX Equalizer Setting mapping in Quartus II software is
incorrect.
--------------------
Issue 8 (case 84782)
--------------------
Can't select /64 refclk frequency for 10312.5Mbps in Stratix V Low
Latency PHY IP from Mega Wizard.
--------------------
Issue 9 (case 84923)
--------------------
PLL code might cause errors in post-fit flow for parameters nreset,
fractional_carryout, and m_cnt_prst. This patch prevents those errors
and recognizes the valid parameter values.
--------------------
Issue 10 (case 85969)
--------------------
Quartus II software might trigger the following internal error in
fitter stage for Partial Reconfiguration revisions:
Internal Error: Sub-system: FITCC,
File: /quartus/fitter/fitcc/fitcc_pr_bits_utility.cpp, Line: 895
pr_region == parent_region_id || parent_region_id == MSF_STATIC_REGION_ID
The problem might occur for PR designs that use both reconfigurable, and
non-reconfigurable LogicLock regions. The error is caused by a false
positive in a post-routing verification step. This patch fixes the
faulty logic in the verification step.
--------------------
Issue 11 (case 81664)
--------------------
Internal Error: Sub-system: ASMDB,
File: /quartus/db/asmdb/asmdb_param.cpp, Line: 522
iter != m_enum_map->end()
--------------------
Issue 12 (case 86164)
--------------------
This patch supports junction temperature QSF settings for Cyclone V
devices.
--------------------
Issue 13 (case 86260)
--------------------
Unexpected signal behavior on the pins within 8A and 8B IOBANK of
Arria V F780 package due to one of the VREF pads not being configured
correctly.
--------------------
Issue 14 (case 86274)
--------------------
This patch provides the following support:
1. Exposes a user-requested ZQ calibration port on UniPHY, similar to
user refresh. The port is activated by setting
alt_mem_if_pingpong_ctl=on, which increases the max pending
read/write commands that can be handled by the controller (for
efficiency reasons).
2. Exposes a set of ports for the refresh controller component. These
ports consist of the tbp_empty, cmd_gen_busy, and
sideband_in_refresh signals. These signals are connected to the
refresh controller by the customer when INI
alt_mem_if_enable_refctrl=on is set.
--------------------
Issue 15 (case 86377)
--------------------
This patch adds support for Arria V 5AGXFB3H4F35C4ES under
dev_password control. Please contact your Altera FAE/AE if you need
this device support.
--------------------
Issue 16 (case 86494)
--------------------
Quartus II software requires a developer license when
RBCGEN_ERROR_TO_CRITICAL_WARNING INI is used.
--------------------
Issue 17 (case 86375)
--------------------
Analog reconfig IP: Preemphasis - pre-tap and 2nd post-tap mappings are
not correct in Quartus II version 12.1.
--------------------
Issue 18 (case 86651)
--------------------
Any Arria V part based on C3 die that uses the right side Levelling
Delay Chains will not function as expected.
Root Cause: Connections from DLL to the Levelling Delay Chains on the
right side were using the wrong DLL output ports.
--------------------
Issue 19 (case 83680)
--------------------
Internal Error: Sub-system: ASMDB,
File: /quartus/db/asmdb/asmdb_offset_cache.cpp, Line: 860
Illegal setting
--------------------
Issue 20 (case 84482)
--------------------
This patch enhances the UniPHY calibration algorithm for all V-series
families. The enhancement adds an extra read calibration after write
calibration, which provides better centering of the read strobe/clock
within the read data window. This enhancement improves robustness at
the highest supported frequencies such as 933MHz DDR3 on Stratix V C2
devices and 800MHz DDR3 on Stratix V 800MHz C3 devices.
=============================================
The following issues are addressed in 0.dp2:
=============================================
--------------------
Issue 21 (case 87286)
--------------------
Internal Error: Sub-system: ASM,
File: /quartus/comp/asm/asm_caddy_base.cpp, Line: 273
block_index != static_cast<DWORD>(-1)
This patch fixes the internal error in Quartus II Assembler for
Stratix V 5SGXA9, 5SGXAB, 5SGXB9, and 5SGXBB devices.
--------------------
Issue 22 (case 87417)
--------------------
This patch enables POF support for Stratix V 5SGSD8 and 5SGSD6
devices.
--------------------
Issue 23 (case 86258)
--------------------
Certain systems are not able to successfully load the USB Blaster II
device driver. If the system error message is 'The parameter is
incorrect', use this updated driver package when re-installing the USB
Blaster II device driver.
--------------------
Issue 24 (case 86633)
--------------------
This patch adds a new stage called "Read Calibration - VFIFO After
Writes" to External Memory Interface debug toolkit.
--------------------
Issue 25 (case 87328)
--------------------
The patch fixes a fatal error in the Quartus II Assembler when user
leaves stratixv_output_alignment.enaoutputcycledelay and
stratixv_output_alignment.enaphasetransferreg ports floated in
non-scan chain mode operation in ALTDQ_DQS2 MegaCore for Stratix V
devices.
*** Fatal Error: Access Violation at 0X00000000015E2DD0
Module: quartus_asm.exe
Lock in use: 9
Stack Trace:
0x22dcf: CDB_SIGNALPROBE_INFO::reset_from_file + 0x123f (db_cdb)
0x3ab56: ASMIO_MODULAR_IO_PIN_MODEL::~ASMIO_MODULAR_IO_PIN_MODEL + 0x11676 (comp_asmio)
--------------------
Issue 26 (case 87329)
--------------------
This patch enables the bus hold circuitry for differential I/O for
Arria V GT devices under INI control. Please contact your Altera
FAE/AE if you need this support.
--------------------
Issue 27 (case 87239)
--------------------
This patch presents the correct sets of fPLLs in floorplans for Stratix V
5SGXEAB, 5SGXEA9, 5SGXMAB, 5SGXMA9, 5SEE9, and 5SEEB devices.
=============================================
The following issues are addressed in 0.dp3:
=============================================
--------------------
Issue 28 (case 86851)
--------------------
This patch fixes DLL to Leveling Delay Chain connectivity on the right
side of the chip for Arria V 5AGXMA1, 5AGXBA1, 5AGXMA3, 5AGXBA3 and
5AGTMC3 devices.
--------------------
Issue 29 (case 86447)
--------------------
This patch exposes dynamic configuration and DLL offset control ports
for Stratix V QDRII with RTL sequencer. This feature is under INI
control. Please contact your Altera FAE/AE if you need this support.
--------------------
Issue 30 (case 87924)
--------------------
This patch removes the minimum frequency restriction from the
ALTDQ_DQS2 IP. This benefits users that want to implement interfaces
below the current minimum frequency, which varies according to device
family.
--------------------
Issue 31 (case 88670)
--------------------
This patch fixes the following internal error in Quartus II Fitter
when compiling xN bonded transceiver designs that involve CGB merging.
Internal Error: Sub-system: HSSI,
File: /quartus/periph/hssi/hssi_reconfig_op.cpp, Line: 5331
atom != 0
Stack Trace:
0xd4313: HSSI::hssi_legality_checker_are_coreclk_connections_valid + 0x69bf3 (periph_hssi)
--------------------
Issue 32 (case 89000)
--------------------
This patch fixes the incorrect JTAG IDCODE for Arria V A3 devices.
--------------------
Issue 33 (case 89148)
--------------------
The patch fixes the bug when the SEU detected by error detection CRC
feature in frame 0 gets masked out by IP as a false positive.
--------------------
Issue 34 (case 89166)
--------------------
This patch adds the PLL phase step signal in timing analysis under INI
control. Please contact your Altera FAE/AE if you need this support.
--------------------
Issue 35 (case 89341)
--------------------
This patch updates the CPRI protocol to meet the 9.8304G datarate for
Arria V GZ Speed Grade -3 devices.
--------------------
Issue 36 (case 83682)
--------------------
This patch fixes PLL reference clock connectivity for Cyclone V
5CEBA2, 5CEFA2, 5CEFA4, 5CEBA4 devices.
--------------------
Issue 37 (case 88292)
--------------------
This patch enables DDR3 LRDIMM PHY and example design generation in
the UniPHY Megawizard.
--------------------
Issue 38 (case 88923)
--------------------
This patch addresses a bug in 12.1 for Stratix V, where the RX offset
cancellation will re-run if the reset signal for the reconfiguration
controller IP is asserted. RX offset cancellation is intended to be
run only once at initial power up and should not have a dependency on
the reset signal.
=============================================
The following issues are addressed in 0.dp4:
=============================================
--------------------
Issue 39 (case 89473)
--------------------
The Quartus II software might trigger the following error in Fitter on
an incremental compilation preserving one or more partitions while
using non-rectangular Logiclock regions.
Error (170070): Cannot place logic cells assigned to one LAB into a
single LAB
This patch fixes the legality check that caused the error.
--------------------
Issue 40 (case 88193)
--------------------
When launching Chip Planner, the Quartus II software might trigger the
following internal error for Arria V designs:
Internal Error: Sub-system: ACVQM,
File: /quartus/ace/acvq/acvqm/acvqm_mapper.cpp, Line: 6517
usage.max_usage should not be zero
--------------------
Issue 41 (case 89402)
--------------------
This patch provides the following support for Cyclone V devices:
1) Enable parts listed below for 5CGX25 device (F23 and U15 packages)
with preliminary pinouts.
5CGXBC3B6F23C7 5CGXBC3B6U15C7 5CGXBC3B7F23C8 5CGXBC3B7U15C8
5CGXFC3B6F23C6 5CGXFC3B6F23C7 5CGXFC3B6U15C6 5CGXFC3B6U15C7
5CGXFC3B7F23C8 5CGXFC3B7U15C8 5CGXFC3B6F23I7 5CGXFC3B6U15I7
5CGXFC3B6U15A7
2) Enable vertical migration support for 5CGX25 devices.
--------------------
Issue 42 (case 89401)
--------------------
For CPRI IP cores that include a MAC Ethernet block and that target
Arria V GZ devices, this patch enables line rates of 9.8304 Gbps.
--------------------
Issue 43 (case 89947)
--------------------
This patch reverts the XAUI interface bus width to/from the
reconfiguration controller IP to 8 for Stratix V devices.
The bus width was changed to 5 in the Quartus II software v12.1 which
caused no-fit failures for designs using the non-bonded workaround or
feedback compensation workaround for XAUI in Stratix V. Bonded
configurations were not affected.
This change is to maintain the backwards compatibility.
--------------------
Issue 44 (case 89780)
--------------------
This patch fixes the VCS compilation failure when ATXPLL is used with
dynamic reconfig enabled.
=============================================
The following issues are addressed in 0.dp5:
=============================================
--------------------
Issue 45 (case 90564)
--------------------
This patch adds the external clocking capability to ALTDQ_DQS2 IP's
capture DDIO and hard read FIFO under INI control. Please contact your
Altera FAE/AE if you need this support.
--------------------
Issue 46 (case 90635)
--------------------
This patch provides the following support for Arria V, Cyclone V, and
Stratix V devices:
(1) Adds support for implicit/explicit user mode OCT
(2) Ensure pre-fitter doesn't merge a user mode OCT block with
non-user mode OCT
(3) Provides option to override specific termination settings under
INI control. Please contact your Altera FAE/AE if you need this
support.
--------------------
Issue 47 (case 90693)
--------------------
HIP block and its reset pin are not correctly associated in Quartus II
device database for Cyclone V. As a result, reset does not work on
hardware for the HIP block when HRC is enabled. With this patch,
placement of reset pin will be correct.
--------------------
Issue 48 (case 90779)
--------------------
Customers who used Quartus II software v12.0SP2 with Stratix V ES
LC's at 12.5G will receive the following compilation error in v12.1:
Error (15004): Can't find the legal settings for PLL node <node name>
because ES silicon LC 14G VCO High Gear is not currently supported.
This patch addresses the issue.
--------------------
Issue 49 (case 91195)
--------------------
This patch enables device migration feature for Cyclone V 5CEA4 and
5CEA2 devices.
--------------------
Issue 50 (case 90746)
--------------------
This patch fixes the configuration failure in JTAG and Passive Serial
modes for Cyclone V E50 devices.
This patch also takes EDCRC bits into IOCSR frame calculation for
Arria V, Cyclone V, and Stratix V devices.
=================
Caution - This patch is not a complete version of the Quartus II
software. You must have previously installed the Quartus II
12.1 before installing this patch.